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Pseudo Differential, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23 AD7453
FEATURES
Specified for VDD of 2.7 V to 5.25 V Low power at max throughput rate: 3.3 mW max at 555 kSPS with VDD = 3 V 7.25 mW max at 555 kSPS with VDD = 5 V Pseudo differential analog input Wide input bandwidth: 70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI(R)/QSPITM/MICROWIRETM/DSP compatible Power-down mode: 1 A max 8-lead SOT-23 package
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+ T/H VIN- VREF
12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK
AD7453
SDATA CONTROL LOGIC CS
03155-A-001
APPLICATIONS
Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation
GND
Figure 1.
PRODUCT HIGHLIGHTS GENERAL DESCRIPTION
The AD7453 is a 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter that features a pseudo differential analog input. This part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 555 kSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier (T/H) that can handle input frequencies up to 3.5 MHz. The reference voltage for the AD7453 is applied externally to the VREF pin and can range from 100 mV to VDD, depending on the power supply and what suits the application. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled on the falling edge of CS; the conversion is also initiated at this point. The SAR architecture of this part ensures that there are no pipeline delays. The AD7453 uses advanced design techniques to achieve very low power dissipation.
1
1. 2.
Operation with 2.7 V to 5.25 V Power Supplies. High Throughput with Low Power Consumption. With a 3 V supply, the AD7453 offers 3.3 mW max power consumption for a 555 kSPS throughput rate. Pseudo Differential Analog Input. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. This part also features a shutdown mode to maximize power efficiency at lower throughput rates. Variable Voltage Reference Input. No Pipeline Delay. Accurate control of the sampling instant via a CS input and once-off conversion control. ENOB > 10 bits Typically with 500 mV Reference.
3. 4.
5. 6. 7. 8.
1
Protected by U.S. Patent Number 6,681,332.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7453 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 AD7453-Typical Performance Characteristics ............................ 9 Circuit Information ........................................................................ 11 Converter Operation.................................................................. 11 ADC Transfer Function............................................................. 11 Typical Connection Diagram ................................................... 12 The Analog Input........................................................................ 12 Digital Inputs .............................................................................. 13 Reference ..................................................................................... 13 Serial Interface ............................................................................ 13 Modes of Operation ....................................................................... 15 Normal Mode.............................................................................. 15 Power-Down Mode.................................................................... 15 Power-Up Time .......................................................................... 16 Power vs. Throughput Rate....................................................... 17 Microprocessor and DSP Interfacing ...................................... 17 Application Hints ....................................................................... 19 Evaluating the AD7453's Performance .................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
2/04--Data Sheet changed from Rev. A to Rev. B Added Patent Note ....................................................................... 1 1/04--Data Sheet changed from Rev. 0 to Rev. A Updated Format..............................................................Universal Changes to General Description ................................................ 1 Changes to Specifications ............................................................ 3 Changes to Timing Specifications .............................................. 5 Changes to Table 4........................................................................ 7 Replaced Figures 11, 12, 13........................................................ 10 Changes to Typical Connection Diagram section ................. 12 Change to Figure 18 ................................................................... 12 Changes to Reference Section................................................... 13 Changes to Timing Example 1.................................................. 14 8/03--Rev. 0: Initial Version
Rev. B | Page 2 of 20
AD7453 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, FIN = 100 kHz, TA = TMIN to TMAX, unless otherwise noted Table 1.
Parameter DYNAMIC PERFORMANCE Signal to Noise Ratio (SNR)2 Signal to (Noise + Distortion) (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay2 Aperture Jitter2 Full-Power Bandwidth2, 3 DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Offset Error2 Gain Error2 ANALOG INPUT Full-Scale Input Span Absolute Input Voltage VIN+ VIN-4 DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 6 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance6 Output Coding Test Conditions/Comments fIN = 100 kHz VDD = 2.7 V to 5.25 V VDD = 2.7 V to 3.6 V VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V; -78 dB typ VDD = 4.75 V to 5.25 V; -80 dB typ VDD = 2.7 V to 3.6 V; -80 dB typ VDD = 4.75 V to 5.25 V; -82 dB typ fa = 90 kHz; fb = 110 kHz A Version1 70 69 70 -73 -75 -73 -75 -80 -80 5 50 20 2.5 12 1.5 0.95 3.5 3 VREF VREF -0.1 to +0.4 -0.1 to +1.5 1 30/10 2.5 5 1 10/30 2.4 0.8 1 10 B Version1 70 69 70 -73 -75 -73 -75 -80 -80 5 50 20 2.5 12 1 0.95 3.5 3 VREF VREF -0.1 to +0.4 -0.1 to +1.5 1 30/10 2.55 1 10/30 2.4 0.8 1 10 Unit dB min dB min dB min dB max dB max dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max V V V V A max pF typ V A max pF typ V min V max A max pF max V min V min V max A max pF max
@ -3 dB @ -0.1 dB
Guaranteed no missed codes to 12 bits
VIN+ - VIN-
VDD = 2.7 V to 3.6 V VDD = 4.75 V to 5.25 V When in track/hold 1% tolerance for specified performance When in track/hold
Typically 10 nA, VIN = 0 V or VDD
VDD = 4.75 V to 5.25 V, ISOURCE = 200 A VDD = 2.7 V to 3.6 V, ISOURCE = 200 A ISINK = 200 A
2.8 2.8 2.4 2.4 0.4 0.4 1 1 10 10 Straight (natural) binary
Rev. B | Page 3 of 20
AD7453
Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD7, 8 Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Mode Test Conditions/Comments 1.6 s with a 10 MHz SCLK Sine wave input Full-scale step input A Version1 16 250 290 555 2.7/5.25 SCLK on or off VDD = 4.75 V to 5.25 V VDD= 2.7 V to 3.6 V SCLK on or off VDD = 5 V; 1.55 mW typ for 100 kSPS7 VDD = 3 V; 0.64 mW typ for 100 kSPS7 VDD = 5 V; SCLK on or off VDD = 3 V; SCLK on or off 0.5 1.5 1.2 1 7.25 3.3 5 3 B Version1 16 250 290 555 2.7/5.25 0.5 1.5 1.2 1 7.25 3.3 5 3 Unit SCLK cycles ns max ns max kSPS max V min/max mA typ mA max mA max A max mW max mW max W max W max
1 2
Temperature ranges as follows: A, B versions: -40C to +85C. See Terminology section. 3 Analog inputs with slew rates exceeding 27 V/s (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the converter. 4 A small dc input is applied to VIN- to provide a pseudo ground for VIN+. 5 The AD7453 is functional with a reference input in the range 100 mV to VDD. 6 Guaranteed by characterization. 7 See Power vs. Throughput Rate section. 8 Measured with a full-scale dc input.
Rev. B | Page 4 of 20
AD7453
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2 and the Serial Interface section. VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter fSCLK1 tCONVERT tQUIET t1 t2 t32 t42 t5 t6 t7 t83 tPOWER-UP 4 Limit at TMIN, TMAX 10 10 16 x tSCLK 1.6 60 10 10 20 40 0.4 tSCLK 0.4 tSCLK 10 10 35 1 Unit kHz min MHz max s max ns min ns min ns min ns max ns max ns min ns min ns min ns min ns max s max Description
tSCLK = 1/fSCLK Minimum quiet time between the end of a serial read and the next falling edge of CS Minimum CS pulse width CS falling edge to SCLK falling edge setup time Delay from CS falling edge until SDATA three-state disabled Data access time after SCLK falling edge SCLK high pulse width SCLK low pulse width SCLK edge to data valid hold time SCLK falling edge to SDATA three-state enabled SCLK falling edge to SDATA three-state enabled Power-up time from full power-down
t1
CS
t2
SCLK 1 2 3 4
t5
5
tCONVERT
B 13 14 15 16
SDATA
0
0 0 4 LEADING ZEROS
0
DB11
DB10
DB2
DB1
DB0
tQUIET
THREE-STATE
Figure 2. AD7453 Serial Interface Timing Diagram
1 2
Mark/space ratio for the SCLK input is 40/60 to 60/40. Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See Power-Up Time section.
Rev. B | Page 5 of 20
03155-A-002
t3
t4
t7
t6
t8
AD7453 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VIN+ to GND VIN- to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial (A, B Version) Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 secs) Infrared (15 secs) ESD Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 10 mA -40C to +85C -65C to +85C 150C 211.5C/W (SOT-23) 91.99C/W (SOT-23) 215C 220C 1 kV
TO OUTPUT PIN 1.6V CL 25pF 200A IOH
03155-A-003
1.6mA
IOL
Figure 3. Load Circuit for Digital Output Timing Specifications
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Transient currents of up to 100 mA will not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 20
AD7453 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1 SCLK 2 SDATA 3 CS 4
8
VREF
Figure 4. Pin Function Descriptions
Table 4. Pin Function Descriptions
Mnemonic VREF
VIN+ VIN-
GND
CS
SDATA
SCLK
VDD
Function Reference Input for the AD7453. An external reference in the range 100 mV to VDD must be applied to this input. The specified reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.1 F. Noninverting Analog Input. Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc offset to provide a pseudo ground. Analog Ground. Ground reference point for all circuitry on the AD7453. All analog input signals and any external reference signal should be referred to this GND voltage. Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7453 and framing the serial data transfer. Serial Data. Logic output. The conversion result from the AD7453 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7453 consists of four leading zeros followed by the 12 bits of conversion data that are provided MSB first. The output coding is straight (natural) binary. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 F capacitor and a 10 F tantalum capacitor.
Rev. B | Page 7 of 20
03155-A-004
VIN+ TOP VIEW 6 VIN- (Not to Scale) 5 GND
7
AD7453
AD7453 TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Full Power Bandwidth Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7453, it is defined as
THD (dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1
as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Aperture Delay The amount of time from the leading edge of the sampling clock until the ADC actually takes the sample. Aperture Jitter The sample-to-sample variation in the effective point in time at which the actual sample is taken.
The full power bandwidth of an ADC is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (000...000 to 000...001) from the ideal (i.e., AGND + 1 LSB) Gain Error This is the deviation of the last code transition (111...110 to 111...111) from the ideal (i.e., VREF - 1 LSB), after the offset error has been adjusted out. Track-and-Hold Acquisition Time The minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal. Power Supply Rejection Ratio (PSRR) The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fS. The frequency of this input varies from 1 kHz to 1 MHz. PSRR(dB) = 10log(Pf/PfS) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fS in the ADC output.
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The AD7453 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is
Rev. B | Page 8 of 20
AD7453 AD7453-TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: TA = 25C, fS = 555 kSPS, fSCLK = 10 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.
75 VDD = 5.25V
1.0 0.8 0.6
70 VDD = 3.6V 65 VDD = 2.7V
DNL ERROR (LSB)
VDD = 4.75V
0.4 0.2 0 -0.2 -0.4 -0.6
SINAD (dB)
60
03155-A-005
03155-A-008
-0.8 -1.0 0 1024 2048 CODE 3072
55 10 FREQUENCY (kHz)
100
277
4096
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
Figure 8. Typical DNL for the AD7453 for VDD = 5 V
0 100mV p-p SINE WAVE ON VDD NO DECOUPLING ON VDD
1.0 0.8 0.6
-20
-40
INL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6
PSRR (dB)
-60 VDD = 3V VDD= 5V -100
03155-A-006
-80
-120 -140 0 100 200 300 400 500 600 700 800 SUPPLY RIPPLE FREQUENCY (kHz)
-0.8 -1.0 0 1024 2048 CODE 3072
900 1000
4096
Figure 6. PSRR vs. Supply Ripple Frequency without Supply Decoupling
Figure 9. Typical INL for the AD7453 for VDD = 5 V
0 -20 8192 POINT FFT fSAMPLE = 555kSPS fIN = 100kSPS SINAD = 71.7dB THD = -82dB SFDR = -83dB
10000 9000 8000 7000 6000 5000
9949 CODES
-40
SNR (dB)
-60 -80
4000 3000 2000
03155-A-007
-100 -120 -140 0 100 200 FREQUENCY (kHz)
1000 27 CODES 0 2046 2047 2048 CODES 24 CODES 2049 2050
277
2051
Figure 7. Dynamic Performance for VDD = 5 V
Figure 10. Histogram of 10,000 Conversions of a DC Input
Rev. B | Page 9 of 20
03155-A-010
03155-A-009
AD7453
4.0 3.5
12 VDD = 3V 11
2.5 2.0 1.5 1.0 0.5 0
03155-A-011
EFFECTIVE NUMBER OF BITS
3.0
CHANGE IN DNL (LSB)
10
9
POSITIVE DNL
8
-0.5 -1.0 0 1 2 VREF (V) 3
VDD = 5V
NEGATIVE DNL 4 5
6 0 1 2 VREF (V) 3 4 5
Figure 11. Change in DNL vs. VREF for VDD = 5 V
Figure 13. ENOB vs. VREF for VDD = 3 V and 5 V
5
4 3
CHANGE IN INL (LSB)
2
1 0
POSITIVE INL
NEGATIVE INL -1
03155-A-012
-2 0 1 2 VREF (V) 3 4 5
Figure 12. Change in INL vs. VREF for VDD = 5 V
Rev. B | Page 10 of 20
03155-A-013
7
AD7453 CIRCUIT INFORMATION
The AD7453 is a 12-bit, low power, single-supply, successive approximation analog-to-digital converter (ADC) with a pseudo differential analog input. It operates with a single 2.7 V to 5.25 V power supply and is capable of throughput rates up to 555 kSPS when supplied with a 10 MHz SCLK. It requires an external reference to be applied to the VREF pin. The AD7453 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface, housed in an 8-lead SOT-23 package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7453 features a power-down option for reduced power consumption between conversions. The power-down feature is implemented across the standard serial interface, as described in the Modes of Operation section. When the ADC starts a conversion (Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and VIN- pins must be matched; otherwise the two inputs have different settling times, resulting in errors.
CAPACITIVE DAC B VIN+ A A B VREF CS SW1 SW3 CONTROL LOGIC SW2 CS COMPARATOR CAPACITIVE DAC
03155-A-015
CONVERTER OPERATION
The AD7453 is a successive approximation ADC based around two capacitive DACs. Figure 14 and Figure 15 show simplified schematics of the ADC in the acquisition and conversion phase, respectively. The ADC is comprised of control logic, an SAR, and two capacitive DACs. In Figure 14 (acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC B VIN+ A A B CS SW1 SW3 VIN- SW2 VREF CS COMPARATOR CAPACITIVE DAC
03155-A-014
VIN-
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7453 is straight (natural) binary. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal transfer characteristic of the AD7453 is shown in Figure 16.
1LSB = VREF/4096
CONTROL LOGIC
111...11 111...10
ADC CODE
111...00 011...11
Figure 14. ADC Acquisition Phase
0V 1LSB
VREF - 1LSB ANALOG INPUT
Figure 16. Ideal Transfer Characteristic
Rev. B | Page 11 of 20
03155-A-016
000...10 000...01 000...00
AD7453
TYPICAL CONNECTION DIAGRAM
Figure 17 shows a typical connection diagram for the AD7453. In this setup, the GND pin is connected to the analog ground plane of the system. The VREF pin is connected to the AD780, a 2.5 V decoupled reference source. The signal source is connected to the VIN+ analog input via a unity gain buffer. A dc voltage is connected to the VIN- pin to provide a pseudo ground for the VIN+ input. The VDD pin should be decoupled to AGND with a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor. The reference pin should be decoupled to AGND with a capacitor of at least 0.1 F. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result.
0.1F 10F +2.7V TO +5.25V SUPPLY SERIAL INTERFACE
R +1.25V 0V -1.25V R VIN 3R R
2.5V 1.25V 0V VIN+
AD7453
0.1F VIN- VREF
EXTERNAL VREF (2.5V)
Figure 18. Op Amp Configuration to Level Shift a Bipolar Input Signal
Analog Input Structure
Figure 19 shows the equivalent circuit of the analog input structure of the AD7453. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward biased and to start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1 in Figure 19, are typically 4 pF and can be attributed primarily to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 . The capacitors C2 are the ADC's sampling capacitors, and have a typical capacitance of 16 pF. For ac applications, removing high frequency components from the analog input signal through the use of an RC low-pass filter on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC, which may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.
VDD
VDD VREF P-TO-P
AD7453
VIN+ SCLK SDATA CS DC INPUT VOLTAGE VIN- VREF GND C/P
0.1F
Figure 17. Typical Connection Diagram
THE ANALOG INPUT
The AD7453 has a pseudo differential analog input. The VIN+ input is coupled to the signal source and must have an amplitude of VREF p-p to make use of the full dynamic range of the part. A dc input is applied to VIN-. The voltage applied to this input provides an offset from ground or a pseudo ground for the VIN+ input. The main benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADC's ground, allowing dc common-mode voltages to be cancelled. Because the ADC operates from a single supply, it is necessary to level shift ground-based bipolar signals to comply with the input requirements. An op amp (for example, the AD8021) can be configured to rescale and level shift a ground-based (bipolar) signal so that it is compatible with the input range of the AD7453. See Figure 18. When a conversion takes place, the pseudo ground corresponds to 0 and the maximum analog input corresponds to 4096.
03155-A-017
2.5V AD780
D VIN+ C1 D R1
C2
VDD
D VIN- C1 D R1
C2
Figure 19. Equivalent Analog Input Circuit. Conversion Phase--Switches Open; Track Phase--Switches Closed
Rev. B | Page 12 of 20
03155-A-019
03155-A-018
AD7453
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 20 shows a graph of the THD versus analog input signal frequency for different source impedances.
0 -10 -20 -30
REFERENCE
An external source is required to supply the reference to the AD7453. This reference input can range from 100 mV to VDD. The specified reference is 2.5 V for the 2.7 V to 5.25 V power supply range. The reference input chosen for an application should never be greater than the power supply. Errors in the reference source result in gain errors in the AD7453 transfer function. A capacitor of at least 0.1 F should be placed on the VREF pin. Suitable reference sources for the AD7453 include the AD780 and the ADR421. Figure 22 shows a typical connection diagram for the VREF pin.
VDD
THD (dB)
-40 -50 -60 -70 -80 -90 10
03155-A-020
AD780
200 100
VDD NC
1 2 VIN 3 TEMP VOUT
AD7453*
NC NC 2.5V NC 0.1F
03155-A-022
OPSEL 8
7 6
VREF
0.1F
10nF
0.1F
4 GND
TRIM 5
-100 10
62
100 INPUT FREQUENCY (kHz)
277
NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. THD vs. Analog Input Frequency for Various Source Impedances
Figure 22. Typical VREF Connection Diagram for VDD = 5 V
Figure 21 shows a graph of THD versus analog input frequency for various supply voltages while sampling at 555 kSPS with an SCLK of 10 MHz. In this case, the source impedance is 10 .
-50 TA = 25C -55 -60 -65
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram of the serial interface of the AD7453. The serial clock provides the conversion clock and controls the transfer of data from the device during conversion. CS initiates the conversion process and frames the data transfer. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. The conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have occurred, the track-and-hold goes back into track mode on the next SCLK rising edge, as shown at Point B in Figure 2. On the 16th SCLK falling edge, the SDATA line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. The conversion result from the AD7453 is provided on the SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7453 consists of four leading zeros, followed by 12 bits of conversion data, provided MSB first. The output coding is straight (natural) binary.
THD (dBs)
-70 -75 -80 -85 -90 10
VDD = 2.7V VDD = 3.6V VDD = 4.75V
03155-A-021
VDD = 5.25V 100 INPUT FREQUENCY (kHz)
277
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
DIGITAL INPUTS
The digital inputs applied to the AD7453 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied, i.e., CS and SCLK, can go to 7 V and are not restricted by the VDD + 0.3 V limits as on the analog input. The main advantage of the inputs not being restricted to the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to VDD.
Rev. B | Page 13 of 20
AD7453
Sixteen serial clock cycles are required to perform a conversion and to access data from the AD7453. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out on the subsequent SCLK falling edges, beginning with the second leading zero. Thus the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that, before the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications. See Timing Example 1. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge, i.e., the first rising edge of SCLK after the CS falling edge would have the leading zero provided, and the 15th SCLK edge would have DB0 provided.
Timing Example 1
Having FSCLK = 10 MHz and a throughput rate of 555 kSPS gives a cycle time of 1/Throughput = 1/555,000 = 1.8 s A cycle consists of t2 + 12.5(1/FSCLK) + tACQ = 1.8 s Therefore if t2 = 10 ns, 10 ns + 12.5(1/10 MHz) + tACQ = 1.8 s tACQ = 540 ns This 540 ns satisfies the requirement of 290 ns for tACQ. From Figure 23, tACQ comprises 2.5(1/FSCLK) + t8 + tQUIET where t8 = 35 ns. This allows a value of 255 ns for tQUIET, satisfying the minimum requirement of 60 ns.
CS 10ns
t2
SCLK 1 2 3 4
t5
5
tCONVERT
13 14 15 16
t6
t8 tACQUISITION
03155-A-023
tQUIET
12.5(1/FSCLK) 1/THROUGHPUT
Figure 23. Serial Interface Timing Example
Rev. B | Page 14 of 20
AD7453 MODES OF OPERATION
The mode of operation of the AD7453 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal mode and powerdown mode. The point at which CS is pulled high after the conversion has been initiated determines whether the AD7453 enters power-down mode. Similarly, if already in power-down, CS controls whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/ throughput rate ratio for differing application requirements.
POWER-DOWN MODE
This mode is intended for use in applications where slower throughput rates are required--the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7453 is in powerdown mode, all analog circuitry is powered down. For the AD7453 to enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 25. Once CS has been brought high in this window of SCLKs, the part enters power-down, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. The time from the rising edge of CS to SDATA three-state enabled is never greater than t8 (see the Timing Specifications). If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. To exit this mode of operation and power up the AD7453 again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after 1 s has elapsed and, as shown in Figure 26, valid data results from the next conversion. If CS is brought high before the 10th falling edge of SCLK, the AD7453 again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it again powers down on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.
CS
NORMAL MODE
This mode is intended for fastest throughput rate performance. The user does not have to worry about any power-up times with the AD7453 remaining fully powered up all the time. Figure 24 shows the general diagram of the operation of the AD7453 in this mode. The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure that the part remains fully powered up, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the 16th SCLK falling edge, the part remains powered up but the conversion is terminated and SDATA goes back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion, or may idle low until some time prior to the next conversion. Once a data transfer is complete, i.e., when SDATA has returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by again bringing CS low.
CS 1 SCLK
03155-A-024
10
16
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 24. Normal Mode Operation
SCLK 12 10
03155-A-025
SDATA
THREE-STATE
Figure 25. Entering Power-Down Mode
Rev. B | Page 15 of 20
AD7453
POWER-UP TIME
The power-up time of the AD7453 is typically 1 s, which means that with any frequency of SCLK up to 10 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed--from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at the maximum throughput rate of 555 kSPS, the AD7453 powers up and acquires a signal within 0.5 LSB in one dummy cycle. When powering up from power-down mode with a dummy cycle, as in Figure 26, the track and-hold, which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 26. Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; 1 s is sufficient to power up the device and acquire the input signal. For example, if a 5 MHz SCLK frequency is applied to the ADC, the cycle time is 3.2 s (i.e., 1/(5 MHz) x 16). In one dummy cycle, 3.2 s, the part is powered up and VIN is acquired fully. However after 1 s with a 5 MHz SCLK, only five SCLK cycles have elapsed. At this stage, the ADC is fully powered up and the signal acquired. So in this case, CS can be brought high after the 10th SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion.
tPOWER-UP
CS A SCLK
03155-A-026
When power supplies are first applied to the AD7453, the ADC may either power up in the power-down mode or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the user wants the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down mode by executing a cycle such as that shown in Figure 25. Once supplies are applied to the AD7453, the power-up time is the same as that when powering up from power-down mode. It takes approximately 1 s to power up fully if the part powers up in normal mode. It is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold is already in track mode. This means (assuming one has the facility to monitor the ADC supply current) that if the ADC powers up in the desired mode of operation and thus a dummy cycle is not required to change the mode, then a dummy cycle is not required to place the track-and-hold into track.
PART BEGINS TO POWER UP
THIS PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED 10 16 1 10 16
1
SDATA
INVALID DATA
VALID DATA
Figure 26. Exiting Power-Down Mode
Rev. B | Page 16 of 20
AD7453
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7453 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 27 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption reduces accordingly. For example, if the AD7453 is operated in continuous sampling mode with a throughput rate of 100 kSPS and a 10 MHz SCLK, and the device is placed in the power-down mode between conversions, then the power consumption is calculated as follows: Power dissipation during normal operation = 7.25 mW max (for VDD = 5 V). If the power-up time is one dummy cycle (1.06 s if CS is brought high after the 10th SCLK falling edge in the cycle and then brought low after the quiet time) and the remaining conversion time is another cycle (1.6 s), then the AD7453 can be said to dissipate 7.25 mW for 2.66 s during each conversion cycle. If the throughput rate = 100 kSPS, then the cycle time = 10 s and the average power dissipated during each cycle is (2.66/10) x 7.25 mW = 1.92 mW For the same scenario, if VDD = 3 V, the power dissipation during normal operation is 3.3 mW max. The AD7453 can now be said to dissipate 3.3 mW for 2.66 s during each conversion cycle. The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore (2.66/10) x 3.3 mW = 0.88 mW This is how the power numbers in Figure 27 are calculated.
100
For throughput rates above 320 kSPS, the serial clock frequency should be reduced for optimum power performance.
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7453 allows the part to be connected directly to a range of different microprocessors. This section explains how to interface the AD7453 with some of the more common microcontroller and DSP serial interface protocols.
AD7453 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the AD7453 without any glue logic required. The SPORT control register should be set up as follows: TFSW = RFSW = 1 INVRFS = INVTFS = 1 DTYPE = 00 SLEN = 1111 ISCLK = 1 TFSR = RFSR = 1 IRFS = 0 ITFS = 1 Alternate Framing Active Low Frame Signal Right Justify Data 16-Bit Data-Words Internal Serial Clock Frame Every Word
To implement power-down mode, SLEN should be set to 1001 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 28. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC, and, under certain conditions, equidistant sampling may not be achieved.
AD7453*
ADSP-21xx*
10
VDD = 5V
SCLK SCLK DR RFS
03155-A-028
POWER (mW)
SDATA
1 VDD = 3V
CS
TFS
0.1
*ADDITIONAL PINS REMOVED FOR CLARITY
03155-A-027
Figure 28. Interfacing to the ADSP-21xx
0.01 0 50 100 150 200 250 THROUGHPUT (kSPS) 300
350
Figure 27. Power vs. Throughput Rate for Power-Down Mode
This figure assumes a very short time to enter power-down mode. This increases as the burst of clocks used to enter power down mode is increased. Rev. B | Page 17 of 20
AD7453
The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and thus the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted or it may wait until the next clock edge. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained and eight master clock periods elapse for every SCLK period. If the timer registers are loaded with the value 803, then 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP.
AD7453*
SCLK
TMS320C5x/ C54x*
CLKx CLKR
SDATA CS
DR FSx FSR
03155-A-029 03155-A-030
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 29. Interfacing to the TMS320C5x/C54x
AD7453 to DSP56xxx
The connection diagram in Figure 30 shows how the AD7453 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement the power-down mode on the AD7453, the word length can be changed to eight bits by setting Bits WL1 = 0 and WL0 = 0 in CRA. For signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provide equidistant sampling.
AD7453*
DSP56xxx*
AD7453 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7453. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7453 without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKx (Tx serial clock) and FSx (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1 and TXM = 1. The format bit, FO, may be set to 1 to set the word length to eight bits in order to implement the power-down mode on the AD7453. The connection diagram is shown in Figure 29. For signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provide equidistant sampling.
SCLK SDATA CS
SCLK SRD SR2
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 30. Interfacing to the DSP56xxx
Rev. B | Page 18 of 20
AD7453
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7453 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the GND pin on the AD7453 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7453 to avoid noise coupling. The power supply lines to the AD7453 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 F tantalum capacitors in parallel with 0.1 F capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.
EVALUATING THE AD7453'S PERFORMANCE
The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7453 evaluation board, as well as many other Analog Devices evaluation boards ending with the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7453. The software allows the user to perform ac (Fast Fourier Transform) and dc (histogram of codes) tests on the AD7453. For more information, see the AD7453 application note that accompanies the evaluation kit.
Rev. B | Page 19 of 20
AD7453 OUTLINE DIMENSIONS
2.90 BSC
8 7 6 5
1.60 BSC
1 2 3 4
2.80 BSC
PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC
1.45 MAX
0.22 0.08 8 4 0
0.15 MAX
0.38 0.22
SEATING PLANE
0.60 0.45 0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 31. 8-Lead Small Outline Transistor Package [SOT-23] (RT-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7453ART-REEL7 AD7453BRT-R2 AD7453BRT-REEL7 EVAL-AD7453CB2 EVAL-CONTROL BRD23 Temperature Range -40C to +85C -40C to +85C -40C to +85C Linearity Error (LSB)1 1.5 1 1 Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 Evaluation Board Controller Board Package Option RT-8 RT-8 RT-8 Branding C0C C09 C09
1 2 3
Linearity error here refers to integral nonlinearity error. This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. For a complete Evaluation Kit, you will need to order the ADC evaluation board, i.e., EVAL-AD7453CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the AD7453 application note that accompanies the evaluation kit for more information.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03155-0-2/04(B)
Rev. B | Page 20 of 20
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